Various applications, such as computer systems, rely on memory devices to store instructions and data that are processed by a microprocessor or CPU. In a typical computer system, the CPU communicates with the memory devices via a CPU bus and a memory controller. The memory devices typically include a dynamic random access memory (DRAM) packaged as a module, such as a single in-line memory module (SIMM) or a dual in-line memory module (DIMM). The memory module typically includes one or more banks of memory chips connected in parallel such that each memory bank stores one set of data, such as a word or double word, per memory address.
The memory controller communicates with, and interprets commands from, the CPU. For example, the CPU issues a command and an address which are received and translated by the memory controller. The memory controller, in turn, applies appropriate command signals and row and column addresses to the memory device. Examples of such commands include a row address strobe (RAS), column address strobe (CAS), write enable (WE), and possibly a clock signal (CLK). (The line or bar over the acronym for a symbol generally indicates that the active state for the particular signal is a logical low value.) In response to the commands and addresses, data is transferred between the CPU and the memory device.
The speed of memory devices has not been able to keep pace with the speed advances in current CPUs. As a result, the speed of current computer systems is limited by the speed in which data and instructions can be accessed from the memory devices of the computer system.
To attempt to keep pace with speed advances in CPUs, faster memory devices have been developed, such as fast page mode (FPM) DRAMs. In most DRAM devices, to limit their size, each memory chip typically includes only enough address terminals to specify either the row address or the column address but not both simultaneously. As a result, the typical memory controller accesses a memory location sequentially by first transmitting the row address and then transmitting the column address. Specifically, the memory controller provides the row address to the memory device, asserts the RAS control signal, then provides the column address on the memory device and asserts the CAS control signal. To ensure proper timing, the memory controller provides a brief delay after asserting the RAS control signal and before asserting the CAS signal (RAS/CAS delay).
The FPM DRAM eliminates the RAS/CAS delay when successive accesses to the same row of memory occur. Because the majority of program execution is sequential in nature, program execution very often proceeds along a row of memory. When in page mode, the memory controller compares the row address of the memory location currently being accessed with the row address for the next memory access. If the row addresses are the same (known as a "page hit"), then the memory controller continues asserting the RAS control signal at the end of a current bus cycle. Because the memory already has the correct row address, the new column address can be immediately transferred to the memory without requiring a RAS/CAS delay.
Extended data out (EDO) DRAMs improve upon the FPM DRAMs. In FPM DRAMs, the CAS high-to-low transition latches the column ddress, while the CAS low-to-high transition turns off an output buffer of the RAM. EDO DRAMs instead separate the two functions of the CAS signal. The low-to-high transition of CAS no longer turns off the output buffer. This change provides an extended time during which the output data is valid, hence the "extended data out" name. EDO memory allows the CPU tp sample the output data even while an address for a subsequent data transfer operation is being set up for the next read cycle.
Burst EDO (BEDO) DRAMs improve upon the good idea used in EDO DRAMs (leaving data valid even after CAS goes high). Most current CPUs typically access BEDO DRAMs in four-cycle bursts at four adjacent memory locations to fill a cache memory. Recognizing this typical access operation, BEDO DRAMs quickly provide the following three addresses itself after receiving the first address. BEDO DRAMs typically include a two-bit counter which provides three column addresses after the first received column address. The memory controller, and CPU, thus avoid the tight timing requirements of providing multiple addresses at appropriate times to the DRAM device. As a result, a "dead" time occurring between the appearance of each bit, byte, word, set or "group" of valid data at the output pins of the BEDO DRAM device is reduced, as compared with respect to EDO and FPM DRAMs. For example, where an FPM DRAM requires an initial five clock cycles to provide a first data group, and three clock cycles for each of three subsequent data groups (i.e., "5-3-3-3 bursting"), BEDO DRAMs can provide bursting at rates of up to 5-1-1-1 or less.
An even faster form of DRAM is synchronous DRAM (SDRAM). FPM, EDO, and BEDO DRAM are asynchronous DRAM devices because they do not require a clock input signal. The memory controller for asynchronous devices receives the system clock signal and operates as a synchronous interface with the CPU so that data is exchanged with the CPU at appropriate edges of the clock signal. Memory controllers for SDRAM devices are necessarily simpler because the SDRAM devices and the CPU both operate based on a clock signal. To achieve optimum performance with a CPU, the SDRAM device must be synchronized with the CPU.
As the speed of DRAM devices increase, other bottlenecks within computer systems arise. For example, as DRAM devices are operated at faster clock rates, the memory controllers to which they are coupled often cannot exchange data between the CPU and the memory device quickly enough.
Additionally, both BEDO DRAM and SDRAM devices require comparatively strict timing requirements compared to FPM and EDO DRAM devices. The strict timing requirements of BEDO DRAM requires a strict relation between generating an edge of CAS and when data is valid for reading or writing to the memory device. During each read cycle, CAS must fall during the middle of the period when data is to be read from the BEDO DRAM. For example, there is very little room for time delay or skew between the system clock and the CAS control signal supplied to the BEDO DRAM when the BEDO DRAM is operated in the 5-1-1-1 burst mode.
As a result, designers must design their computer systems, or other applications, with minimum trace lengths on circuit boards to reduce propagation delays, and employ other methods to minimize skew between the system clock and command signals based on the clock. One memory controller chip set by Intel is believed to accommodate BEDO DRAM; however, such a chip set likely still requires the designer to be subject to the strict timing requirements of BEDO memory. Similarly, SDRAM devices require strict timing of data transfers with the SDRAM device in relation to the system clock signal. As a result of such strict requirements of BEDO DRAM and SDRAM devices, computer system designers and other users of DRAM devices have difficulty implementing such higher speed DRAM devices into their applications, despite the increased performance of such devices. As a result, system designers have accepted and employed lower speed DRAM devices in exchange for looser timing requirements in their designs, despite the speed and other benefits of BEDO and SDRAM devices.